Dynamic random access memories (DRAMs) use charge which can be stored and read on a storage capacitor in a cell array of the DRAM to characterize a digital state, for example a “1” or a “0”. The charge which can be stored on the storage capacitor is supplied and removed by a flow of current via a select transistor. The select transistor used is usually a MOSFET (metal oxide semiconductor field effect transistor), the conductivity of which is controlled, in a channel region formed in the semiconductor body of the DRAM, by field effect via a gate conductor structure which is electrically separated from the channel region by a gate insulator structure. The channel region is located between semiconductor zones formed as source and drain regions in the semiconductor body. One of the semiconductor zones is electrically connected to the storage capacitor, and its connection region to the corresponding semiconductor zone is referred to as the node contact (CN: Contact Node). The other of the two semiconductor zones is connected via a bit line contact (CB: Contact Bit Line) to a bit line which is formed in a metallization level, for example a M0 level, and conductively connects the select transistor to an evaluation circuit, for example to a sense amplifier in a support region of the DRAM. The DRAM usually has a plurality of select transistors which are arranged in rows and columns and can be individually driven via the bit lines and gate conductor structures in the form of word lines.
DRAM semiconductor memory components are usually designed with a trench capacitor or stack capacitor for storing charge. In the case of the trench capacitor, the storage capacitor is formed in a trench which extends into the semiconductor body, while in the case of stack capacitors the storage capacitor is formed above the semiconductor body in a wiring region for connection of the semiconductor components in the semiconductor body. A conductive connection between the storage capacitor and the node contact of the select transistor is provided by a contact structure for the storage capacitor (CC: Contact Capacitor).
At present, in the known fabrication of stack DRAMs, first of all M0 tracks, i.e. bit lines, are fabricated, followed by the contact structures for the storage capacitor being formed in self-aligned fashion with these tracks. A procedure of this type is subject to restrictions in terms of the width and thickness of the bit lines, since after the bit lines have been formed, a nitride cap usually serves as a spacer (nitride spacer) for subsequent contact hole patterning for connection of the storage capacitor. This step is carried out as a self-aligned etching step (SAC etch with the nitride cap as mask) and is difficult to implement in terms of process engineering. The nitride spacer also leads to undesirably greater capacitive coupling between the bit lines and the contact structure for the storage capacitor compared to an oxide, such as SiO2. This is attributable to the higher dielectric constant of silicon nitride (εr≈7 for Si3N4) compared to oxide (εr≈3.8 for SiO2). Since to form the contact structure for the storage capacitor, it is necessary to etch through an interlayer dielectric, for example an M0 oxide, formed between the bit lines, the choice of material for the interlayer dielectric is considerably restricted by its etching properties for the formation of the contact structure.